1. Field of the Invention
The present invention relates to a method and apparatus for coating a substrate surface such as a semiconductor wafer or liquid-crystal display (LCD) glass substrate surface, with a resist liquid and developing the substrate after exposure thereof to light. The invention also concerns a storage medium used for these coating and developing operations.
2. Description of the Related Art
In a photoresist process that is one of semiconductor-manufacturing processes, the surface of a semiconductor wafer (hereinafter, also referred to simply as a wafer) is coated with a resist, and then after exposure of this resist on the wafer to light with a required pattern, the wafer is developed to form a resist pattern on the surface thereof. Such processing generally uses a system that has an exposure apparatus connected to a coating and developing apparatus for resist-coating and developing wafers.
As described in JP-A-2006-253501, for example, a known coating and developing apparatus includes a carrier block into which a carrier containing a plurality of semiconductor wafers is loaded, an interface block for transferring each wafer to and from an exposure apparatus, and a processing block provided between the carrier block and the interface block.
The processing block includes a coating block in which a coating (COT) module for coating the wafer with a resist is included, and a developing block in which a developing (DEV) module for supplying a developing agent to and developing the resist-coated wafer is included. The coating block and the developing block are arranged in layers. The coating block and the developing block include a heating module and a cooling module, respectively, to heat and cool the wafer before and after its resist-coating and developing steps. Both the coating block and the developing block also include an arm for conveying the wafer from one module to another module.
For improved throughput, the coating module, the developing module, the heating module, the cooling module, and other process modules for processing wafers are each provided in a plurality of places in the coating block and the developing block. Wafers that have been sequentially unloaded from the carrier are each conveyed to an empty process module having no wafers loaded thereinto, and undergo concurrent processing in each process module. After this, each processed wafer is sequentially unloaded from each process module into empty process modules provided at the next stage.
FIG. 13 shows the modules in the coating and developing apparatus, and a conveying route of wafers between the modules. A wafer that has been unloaded from the carrier 101 is conveyed to a transfer (TRS) stage 103 by a carrier arm 102 provided in the carrier block described above. After that, the wafer is conveyed first to a transfer arm 104 that moves vertically in the processing block, and then to a TRS stage 105.
After this, the wafer is further conveyed to a coating block, in which the wafer is then transferred to an adhesion (ADH) process (hydrophobizing) module 107A or 107B, a cooling module 108A or 108B, a COT module 109A, 109B, or 109C, either of heating modules 110A to 110D, a wafer edge exposure (WEE) module 111, and a buffer module 112, in that order, by a dedicated conveyance arm 106 for the coating block.
After that, the wafer is conveyed to an exposure apparatus 113 via the transfer arm 104, a shuttle arm 112 that moves from the carrier block to the interface block, and an interface arm 114 within the interface block, in that order, and is exposed to light.
The exposed wafer is conveyed to a TRS stage 115A or 115B via the interface arm 114. After this, the wafer is further conveyed to either heating module from 117A to 117F, a cooling module 118A or 118B, either DEV module from 119A to 119F, either heating module from 120A to 120F, and a TRS stage 121A or 121B, in that order, by a conveyance arm 116 provided in the developing block. The wafer is returned to the carrier 101 after that.
Further improving the throughput of such a coating and developing apparatus is under consideration to achieve a target throughput of, for example, about 200 to 300 wafers per hour (3,600 seconds). To achieve the throughput of 200 wafers per hour, the above coating and developing steps need to be performed at a rate of 3,600 seconds/200 wafers=18 seconds/wafer. To achieve the throughput of 300 wafers per hour, the coating and developing steps need to be performed at a rate of 3,600 seconds/300 wafers=12 seconds/wafer.
If the conveyance of one wafer from a module of the immediately previous stage to a module of the immediately following stage is counted as one conveying operation, the conveyance arm 106 repeats the conveying operation a total of six times in the coating block to move the wafer from the TRS stage 105 to the buffer module 112. In order to achieve the above throughput values, therefore, the intermodule conveyance time per operation is set to be a maximum of 18 seconds/6=3 seconds for the throughput of 200 wafers/hour, or a maximum of 12 seconds/6=2 seconds for the throughput of 300 wafers/hour.
To convey the wafer at such a speed, it becomes necessary to specify the wafer conveyance destination so that upon completion of processing in one module, the wafer can be immediately conveyed to the next module. Therefore, installing each module in a larger number of places in the coating and developing blocks and increasing the number of wafers to undergo concurrent processing in modules of the same kind is considered. FIG. 14 shows an example in which the number of modules of the same kind in the coating block is increased.
However, there is the problem that for example, if the conveying speed of the conveyance arm 106 is raised to allow intermodule conveyance within 2 or 3 seconds for improved throughput, an increase in load of the conveyance arm 106 could be more likely to cause a conveying error such as a fall of the wafer from the conveyance arm 106 during conveyance. A method of solving this problem is not described in above-mentioned JP-A-2006-253501.